The following table contains known issues, scheduled bug fixes, and feature improvements for the Verdin iMX95.
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Customer Impact: Customers may observe unreliable or failed Ethernet PHY communication on carrier-board second Ethernet interfaces when using certain PHY devices connected to the shared MDIO bus. Symptoms can include PHY initialization failures, inability to detect the PHY correctly, or unexpected MDIO register access affecting multiple PHYs simultaneously.
Description: The SoM Ethernet PHY uses SMI address 0 (unicast), and the MDIO bus is shared between the SOM and the carrier board. Because of that it is not possible to use an Ethernet PHY on the carrier board that honors the 0 SMI broadcast address.
Workaround: Do not use Ethernet PHYs on the carrier board that respond to MDIO/SMI address 0 as a broadcast address. When designing carrier boards for Verdin iMX95, ensure all external Ethernet PHYs are configured to use non-zero MDIO addresses and that selected PHY devices do not treat address 0 as broadcast on a shared MDIO bus.
Customer Impact: Customer circuits implemented on the carrier board that rely on the CTRL_RESET_MOCI signal for delayed start-up may not operate as intended.
Description: Due to the PMIC’s internal logic, the CTRL_RESET_MOCI signal is asserted high immediately after all power rails have been raised. Not waiting until the CTRL_RESET_MICO will go High.
Workaround: Will be fixed in V1.1
Customer Impact: Designs utilizing the CTRL_FORCE_OFF_MOCI# signal to control system power rails are impacted. Following either a long power-button press or a software-initiated power-down request from the SoC, the CTRL_FORCE_OFF_MOCI# signal remains asserted High and does not transition Low as expected.
Description: An error in the schematic of the SoM causes the wrong behaviour of the CTRL_FORCE_OFF_MOCI# signal.
