 HAR-11013 | Known Issue | Possible Noise on Audio Output during Reset Cycle | Colibri iMX6S
Colibri iMX6DL | |
Description: The audio codec on the SGTL5000 on the module does not feature a dedicated reset input. If a sound is playing back during a reset cycle, the SGTL5000 remains in playback mode. The audio codec is then repeating the last short sample which is remains in its buffer. This creates an audible noise at the output. The actual noise depends on the sample which is in the buffer. This noise is retained until the audio codec is reinitialized during the booting process.
The issue only appears if the reset is initiated by the RESET_MICO# reset (e.g. pressing reset button on evaluation board). The effect has not been seed during software initiated reset cycles or regular power cycles. Workaround: There is currently no workaround available. Try to avoid pressing the reset button while any sound is played back from the on module audio codec. |
| HAR-11012 | Known Issue | Possible short pulse on nRESET_OUT if nRESET_EXT is hold down | Colibri iMX6S 256MB IT V1.1A WinEC
Colibri iMX6DL 512MB IT V1.1A WinEC
Colibri iMX6DL 512MB V1.1A WinEC
Colibri iMX6S 256MB V1.1A WinEC | |
Description: The nRESET_EXT (reset input of the module, pin 26) features a debouncing circuit since it is allowed to connect directly a reset button to this pin. The debouncing circuit delays the reset by around 30ms. During a regular power up sequence, the nRESET_OUT (reset output of the module, pin 87) is released also at around 30ms. If the nRESET_EXT pin is hold down during the power up, the two delays are racing. If the debouncing circuit wins, everything is OK, the nRESET_OUT remains until the nRESET_EXT is released. However, if the debouncing loses the race, there can be as short peak on the nRESET_OUT.
Whether this peak appears or not as well as the duration depends on different factors. It is depending on the tolerances of the debouncing circuit and therefore can appear on certain modules more often than on others. It also depends on the module temperature and whether an RTC battery is present or not. Workaround: The Colibri iMX6 module as well as most of the peripheral devices are not affected by the possible nRESET_OUT pulse. This means in most of the cases, the issue can be ignored. For peripherals that relay on a single reset release during the power up sequence, an additional circuit is required on the carrier board. Such a circuit can be a simple AND gate with the NRESET_OUT and nRESET_EXT as inputs can be used. |
| HAR-11011 | Known Issue | Secure Boot Vulnerabilities (NXP ERR010872 and ERR010873) | Colibri iMX6S 256MB IT V1.1A WinEC
Colibri iMX6DL 512MB IT V1.1A WinEC
Colibri iMX6DL 512MB V1.1A WinEC
Colibri iMX6S 256MB V1.1A WinEC | |
Description: These errata are actually NXP errata affecting all i.MX and Vybrid processors. There are two issues in the boot rom when using the processors in a security enabled configuration (SEC_CONFIG[1] eFUSE is programmed). By default, this fuse is not programmed on Toradex modules. Customers not fusing this setting are therefore not affected by these issues.
Customers using the security enabled configuration are affected by these issues. More information can be found in the respective NXP errata documents:
https://docs.toradex.com/104705-err010872-secure-boot-vulnerability-erratum-preliminary-rev0.pdf
https://docs.toradex.com/104706-err010873-secure-boot-vulnerability-erratum-preliminary-rev0.pdf Workaround: Please refer to the above-mentioned documents for workarounds. |
| HAR-11008 | Known Issue | Software initiatated reset cycle does not assert nREST_OUT | Colibri iMX6 V1.0 | Colibri iMX6 V1.1 |
Description: During a software initiated reset cycle, the nRESET_OUT signal is not asserted on the Colibri iMX6 V1.0 module. Unlike other Colibri modules, the nRESET_OUT signal remains the whole time high during the software initiated reset.
During power up as well as hardware initiated reset cycles (by pressing the nRESET_IN/RESET_EXT button), the nRESET_OUT signal gets asserted similar to other Colibri modules. This is not an issue as long as external peripheral devices on the carrier board do not need to be reset during a software reset or no software initiated reset cycles are used on a system. Workaround: A possible workaround is implementing a small reset circuit on the carrier board that allows driving low the reset signal by using any free GPIO.
Since on the Colibri iMX6 the reset state of regular GPIOs is configured as input with enabled internal pull up resistor, the transistor will pull down the reset line during a software initiated reset cycle. The bootloader or application needs to reconfigure the GPIO as output and drive it low for releasing the external reset signal. |
| HAR-11007 | Known Issue | Module cannot wake up from PMIC shutdown mode | Colibri iMX6 V1.0 | Colibri iMX6 V1.1 |
Description: If a module shut down is proceeded by the software which turns off the power management IC (PMIC), the module can only be restarted again if all power rails are removed (including VCC_BATT) and reapplied. This means, as long as the RTC is running (VCC_BATT available), the module cannot be started. All other sleep modes of the modules are not affected by this issue. Workaround: Do not shut down the PMIC. The current Linux and Windows CE image take this in account. They leave the PMIC running after finishing the software shut down request. The module main input rail can be removed without issue as long as no PMIC shut down request was executed. In most systems, the PMIC shut down is not needed. The Colibri module concept does anyway not implement a shutdown mode similar to the “Soft-Off-Modus” S5 that is known from the ACPI specifications (https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface). |
| HAR-9467 | Known Issue | SkyHigh eMMC's not properly initialized when booted from other media in pSLC mode Colibri iMX6 | Colibri iMX6S 256MB V1.1A
Colibri iMX6DL 512MB V1.1A
Colibri iMX6S 256MB V1.1B WinEC
Colibri iMX6S 256MB V1.1Y WinEC
Colibri iMX6DL 512MB V1.1B WinEC
Colibri iMX6DL 512MB V1.1Y WinEC | Colibri iMX6S 256MB V1.1A
Colibri iMX6DL 512MB V1.1A
Colibri iMX6S 256MB V1.1B WinEC
Colibri iMX6S 256MB V1.1Y WinEC
Colibri iMX6DL 512MB V1.1B WinEC
Colibri iMX6DL 512MB V1.1Y WinEC |
Customer Impact: When configuring and using the SkyHigh eMMC in MLC mode customers are not affected. Customers using pSLC (pseudo-SLC) mode and trying to boot from SD card the module may not work. Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and trying to boot from SD card the module may not work. Workaround: There are three possible workarounds:
1) Access the eMMC from U-Boot before launching the Kernel by using the following command: ls mmc 0.4:0 /boot
2) Update the eMMC firmware according to the instructions:
https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc
3) Modules produced after 09.12.2022 are not affected |
| HAR-9446 | Known Issue | STMPE811 ADC can get wrongly strapped if voltage is applied to ADC_AD1 input during boot | Colibri iMX6 V1.1
Colibri iMX6 V1.0 | Not applicable |
Customer Impact: If voltage is applied to ADC_AD1 input during boot, the ADC inputs and the touch interface may not work as the STMPE811 is not accessible on the I2C bus. Description: The STMPE811 ADC and touch controller IC uses the IN0_GPIO1 pin for strapping between I2C and SPI mode. If the pin is high during the power-up of the controller, the chip gets misconfigured as an SPI device. In this case, the chip cannot be accessed over the I2C mode and is unavailable.
The IN0_GPIO1 is used as ADC_AD1 input of the module (edge connector pin 6). A voltage applied to the analog input ADC_AD1 during the module's power-up can cause the ADC and touch controller to be strapped wrongly and therefore not accessible.
The module features a circuit that pulls down the ADC_AD1 input during the reset state to prevent false strappings. However, this circuit may not work correctly if there is extensive backfeeding to the module. The best prevention is not applying any voltage to the ADC_AD1 input while the module is not powered. Workaround: Ensure that there is no voltage applied to the ADC_AD1 input until the module booted. Use any of the other ADC inputs instead. |
| HAR-9438 | Known Issue | Endurance degradation of Colibri iMX6 modules with the SkyHigh eMMC in pSLC mode | Colibri iMX6S 256MB V1.1A
Colibri iMX6DL 512MB V1.1A
Colibri iMX6S 256MB V1.1B WinEC
Colibri iMX6S 256MB V1.1Y WinEC
Colibri iMX6DL 512MB V1.1B WinEC
Colibri iMX6DL 512MB V1.1Y WinEC | Colibri iMX6S 256MB V1.1A
Colibri iMX6DL 512MB V1.1A
Colibri iMX6S 256MB V1.1B WinEC
Colibri iMX6S 256MB V1.1Y WinEC
Colibri iMX6DL 512MB V1.1B WinEC
Colibri iMX6DL 512MB V1.1Y WinEC |
Customer Impact: Using the SkyHigh eMMC based module in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, will lock up the device, not allowing any further writes to the eMMC. Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, the eMMC firmware will lock up the device, not allowing any further writes to the eMMC. The theoretical lifetime data write capacity for SkyHigh eMMCs in pSLC mode would be 60TB. By default, Toradex doesn't enable the pSLC mode and therefore doesn't run into this problem. Workaround: SkyHigh implemented an FW fix. Customers using pSLC mode and writing more than 32TB during the lifetime of the product can execute a single-step FW update: https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc
Products produced after 09.12.2022 are not affected |
