The following table contains known issues, scheduled bug fixes, and feature improvements for the SMARC iMX95.
For other information, click on the below links:
Customer Impact: JTAG debugging and Boundary Scan not working.
Description: There is a conflict on the TCK and TDI signals because they are shared with the BT UART signals. JTAG debugging and Boundary Scan only work if the R59 and R60 resistors are removed.
Customer Impact: Customers using SMARC iMX95 V1.0 with SMARC Development Board V1.0 or V1.1A will find that connected DisplayPort monitors are not detected.
Description: A design issue in the DisplayPort interface of the SMARC iMX95 V1.0 employs a pull-down resistor that is too low to provide the required signal level, when combined with SMARC Development Board V1.0 or V1.1A. In the SMARC Development Board V1.1B, the pull-up strength has been increased to mitigate the issue. The next SMARC iMX95 V1.1 will comply with the SMARC Standard.
Workaround: Customers could replace the 100k Pull-up resistor - R59 with a 10K resistor in the SMARC Development Carrier board V1.0 and V1.1 to get the interface to work with SMARC iMX95 V1.0.
Customer Impact: The GPIO pins without pull-up resistors might cause unpredictable behavior.
Description: There are missing pull-up resistors on GPIO pins connected to SoM GPIO Expander. Those pins are not in line with the SMARC requirements
Description: Footprint for USB_EN_OC# buffer/line driver is wrong
Customer Impact: PCIE Ref Clk - Ethernet reference oscillator doesn't work due to wrong supply voltage
Description: The LMK6HA15625ADLER oscillator does not generate any output.
Customer Impact: Ethernet interface ETH_PHY1 will not support interrupt-driven operation due to hardware limitations in the PCAL64xx I/O expander and the shared interrupt line configuration. As a result, ETH_PHY0 continues to operate normally with interrupt support while ETH_PHY1 must rely on polling mode instead of interrupts.
Description: Slightly higher CPU utilization due to continuous status polling. Potentially increased latency in link status changes or event detection on ETH_PHY1. Despite this, overall Ethernet functionality remains available on both PHYs.
