Hardware Release

Description: On 20.07.2020 we were informed about an LVDS instability issue (flickering) on new version of NXP i.MX 8QuadXPlus/i.MX 8DualXPlus which are used in our prototype Apalis iMX8X products until version 1.1A. The LVDS display interface clock might not run stable depending on temperature and voltage applied.

Workaround: We are working with NXP to get screened processors that do not manifest this issue. This issue will be fixed in the next product version.

Description: The RX and TX signals of the I2S audio interface between the i.MX 8M Plus SoC and the Wi-Fi module are swapped.

Workaround: There is no workaround for making the Bluetooth audio feature of the Wi-Fi module available.

Description: The Verdin pinout contains an optional master clock output for the CSI_1 interface. The SAI3_MCLK SoC pin is used for providing the optional Verdin camera interface master clock CSI_1_MCLK output. This signal is available on the module edge connector pin 91. The SoC pin can provide clock signals from the SAI3 and SAI5 audio interfaces. Therefore, a dummy audio driver with a dummy audio stream would be required for enabling the clock output. The current Toradex BSP does not support the CSI_1_MCLK option.

Workaround: Instead of using the CSI_1_MCLK, use an external crystal or oscillator for the camera. The i.MX 8M Plus SoC features two general-purpose clock outputs that can be used independently from the audio interfaces. Those clock signals are only available as alternate functions of other signal pins. Therefore, the clock signals are not compatible with other Verdin modules. If one of the general purposes clock outputs are used, adding an assembly option for using the CSI_1_MCLK pin is highly recommended. This ensures compatibility with existing and future versions of the Verdin iMX8M Plus and other Verdin modules.

Description: The signal used for strapping the HCI (Host Controller Interface) configuration of the Bluetooth solution at the time of powering up the SoM is also available on the Module-specific pin MSP_8 (#104) of the SoM edge connector. Module-specific pins feature stitching capacitors for providing current return paths for cases when those pins are being used for accommodating high-speed signals. The Verdin iMX8M Plus V1.0B configurations equipped with a Wi-Fi/Bluetooth solution feature one such capacitor (C210) on the MSP_8 signal. During powering up the system, the stitching capacitor is delaying the transition of the related signal to the intended state and thus results in a wrong configuration being strapped. Instead of SDIO mode, the host interface of the Bluetooth solution gets configured to UART mode. As a result, the Bluetooth solution is not accessible by the system.

Workaround: Remove the stitching capacitor C210 from the SoM. This makes the Bluetooth interface work in case the SoM is connected to a Dahlia V1.1A carrier board. If the SoM is connected to a Verdin Development Board V1.1A, then other stitching capacitors need to be removed from the carrier board as well. For more information, please refer to HAR-8342 in the Verdin Development Board errata. The issue will be resolved in future HW versions of these products.

Description: For the dual stacked USB host connector (X53), the assignments of the upper and lower ports and the related power status indication LEDs are swapped. LED5 is indicating the power status of the lower port, while LED4 is indicating the power status of the upper port. The silkscreen is going to be updated in a future product version.

Workaround: There is no workaround to the issue.

Description: According to the PCIe specifications, software needs to wait a minimum of 100ms before sending a configuration request to a PCIe device after enabling the power and the clock. The Verdin specification provides a dedicated reset signal for the PCIe interface (PCIE_1_RESET#). The Verdin Development Board features an RC delay circuit on this signal. This circuit consists of a 10uF capacitor and a 10kOhm pull-up resistor, resulting in a time constant of 100ms. The actual time it takes for the device to get out of the reset state is influenced by the threshold level of the device's reset input and component tolerances as well. These factors together make the timing unpredictable. As a consequence, a PCIe device may still be in the reset state when the driver is sending the first configuration requests. The issue does not necessarily manifest in case of all potential PCIe devices, and can be temperature-dependent as well.

Workaround: By eliminating the RC delay circuit from the reset signal, the module's reset timing can be fully controlled by the PCI_1_RESET# signal. For achieving that, remove the 10uF capacitor C173. The change prevents the described issue from happening. The change is going to be implemented in future versions of the product. Alternatively, the delay between releasing the reset and initiating the configuration requests can be increased in the driver. However, this is not the preferred method as this requires modifications to be done to the standard drivers.

Description: The signal used for strapping the HCI (Host Controller Interface) configuration of the Bluetooth solution at the time of powering up a Verdin iMX8M Plus SoM is also available on the Module-specific pin MSP_8 (#104) of the SoM edge connector. Module-specific pins feature stitching capacitors for providing current return paths for cases when those pins are being used for accommodating high-speed signals. The Verdin Development Board V1.1A features two such capacitors (C250, C313) on the MSP_8 signal. During powering up the system, the stitching capacitors are delaying the transition of the related signal to the intended state and thus result in a wrong configuration being strapped. Instead of SDIO mode, the host interface of the Bluetooth solution gets configured to UART mode. As a result, the Bluetooth solution is not accessible by the system.

Workaround: Remove the stitching capacitors C250 and C313 from the carrier board. This makes the Bluetooth interface work in case the carrier board is connected to a Verdin iMX8M Plus SoM with a hardware version of V1.0C or newer. If the carrier board is connected to a Verdin iMX8M Plus V1.0B, then another stitching capacitor needs to be removed from the SoM as well. For more information, please refer to HAR-8341 in the Verdin iMX8M Plus errata. The issue will be resolved in future HW versions of these products.

Description: The MAYA-W1 Wi-Fi module's datasheet was updated revising the maximum input voltage rating, before Toradex released Verdin AM62 V1.2 products. The absolute maximum input voltage has been adjusted from 6.5V down to 4.2V. Unfortunately, this change affects some Verdin AM62 modules (specifically, the Solo 512MB WB IT V1.1 0072, Dual 1GB WB IT V1.1 0074, and Quad 2GB WB IT V1.1 0076), as they directly power the Wi-Fi module from the module input voltage. The Verdin input voltage range is officially specified as 3.135V to 5.5V. The issue lies in the carrier board’s power supply to the module. While the Dahlia carrier board adheres to 3.3V voltage, other boards (Verdin Development Board, Mallow, Yavia, and Ivy) provide 5V, exceeding the Wi-Fi module’s specifications. Additionally, any customer-designed carrier boards that exceed 4.2V are also affected. The Verdin AM62 V1.2 has been updated to power the MAYA-W1 Wi-Fi module from a regulated 3.3V rail. This means Verdin AM62 modules with version 1.2 and newer are not affected by the issue and can be powered with input voltages up to 5.5V without any issue. Modules without Wi-Fi/Bluetooth are not affected by this errata.

Workaround: To mitigate this issue, consider the following countermeasures: For Verdin AM62 V1.1 modules, ensure that the module input voltage remains below 4.2V. Currently, the Dahlia carrier board is the only Verdin family carrier board provided by Toradex that adheres to this limitation by providing 3.3V. Avoid turning on the Wi-Fi or Bluetooth radio while the module is powered with an input voltage higher than 4.2V. During evaluation, it’s possible to operate the Wi-Fi module with voltages between 4.2V and 5.5V. However, please be mindful of the potential impact on long-term reliability or damage. Toradex has not observed any damaged Wi-Fi modules in their in-house tests, which span multiple days and include extreme temperature conditions. It’s important to note that this practice deviates from the official MAYA-W1 specifications and is not recommended for use in final products. For optimal performance and reliability, we recommend a transition to the Verdin AM62 V1.2 modules (when they become available). These newer modules power the MAYA-W1 Wi-Fi module from a regulated 3.3V rail and are not affected by the issue described in this errata.

Description: A few Verdin AM62 are affected by a soldering issue on an LDO that generates the 1.0V voltage for the Texas Instruments DP83867IR Ethernet Transceiver. In this situation, the Gigabit Ethernet interface of the module might not work reliably. The module RGMII interface is not affected by this errata. This interface can be used to evaluate the module network functionalities.

Workaround: If your module is affected by this errata, please contact the Toradex RMA department. This issue will be fixed in future product revisions.

Description: SoMs inserted on Mallows may have problems reading EDID on multiple displays using native HDMI due to a bidirectional level shifter in the DDC circuit causing interference.

Workaround: There is no known workaround besides assembling an alternative bidirectional level shifter. This issue will be fixed in future product versions.

Description: The WAKE1_MICO# signal is used to wake up the Apalis SoMs from the suspend state (sleep state). This signal is served with a regular GPIO (with wake capability). The IO rail of this GPIO is turned off during the off state. Therefore, by design, it is not possible to use the WAKE1_MICO# signal for waking the SoM up from the off state (the SoM can only be woken up from the off state by asserting the RESET_MICO# signal or via a complete power cycle). In the affected HW versions of the Ixora, the WAKE1_MICO# signal is pulled up to the 3.3V (always-on) rail. The 3.3V (always-on) rail remains on, even if the SoM is shut down (off state). As the IO rail of the GPIO pin serving the WAKE1_MICO# signal is turned off during the off state, a small backfeeding current can occur in the off state from the pull-up resistor on the carrier board into the SoM/SoC. For the above reasons, it is recommended to pull up the WAKE1_MICO# to the 3.3V_SW (switched), which is turned off in the off state.

Workaround: The 10kOhm pull-up resistor on the carrier board (R146) can be removed, if the related internal pull-up resistor of the SoC is enabled or the wake function is entirely disabled. This eliminates the potential backfeeding over the WAKE1_MICO# signal.

Description: The RS232 port of the host computer is backfeeding to the Iris carrier board and the SoM through the RS232 transceiver. For example, in combination with the Colibri iMX6 module, a residual voltage of around 0.7V can be measured at the 3.3V rail while only the RS232 cable is connected to the carrier board.

Workaround: Consider replacing the RS232 transceiver (IC4 and/or IC6 on the Ixora) with a footprint-compatible part. Some of the alternative transceivers not prone to backfeeding: TI TRS3243EIDBR, TI MAX3243IDB, ST ST3243EBTR.

Description: If only the USB client cable is plugged in while all other power sources are removed, the USB power switching IC1 gets enabled and disabled periodically. The enable input of the power switch IC is active low. If the power rails are removed, the USB_P_EN signal goes slowly down, which at one point enables the USB power switch. This unintentionally powers the board from the USB source through the 5V buck converter and turns on the 3.3V buck regulator. Since the 3.3V rail is up, the USB_P_EN signal also goes high and disables the USB power switch. This cycle repeats continuously and makes the power LEDs blinking.

Workaround: Remove the resistor R156 and assemble the resistor R157 instead. This prevents the continuous power cycles from starting since the USB power switch and the buck converters remain powered down. The backfeeding protection circuit inside the USB power switch (IC1) works and disables the switch regardless of the USB_P_EN signal level.

Description: The issue affects about 4% of the Iris V1.1A carrier boards shipped before the 30th of October 2015 and is caused by a broken capacitor (C55). It is possible to check the RTC circuit current consumption by measuring the voltage across a shunt resistor connected in series with the power supply used to provide 3.3V on the battery holder positive pin. The normal RTC standby supply current should be around 1uA.

Workaround: Customers who received products before the 30th of October 2015 and use the RTC circuit should measure the current consumption on already received products. If an abnormal current consumption is detected, contact the Toradex RMA department to get the board fixed or replaced. Our testing process has been adjusted to find the mentioned problem and rework the affected products.

Description: Due to a race condition between the pull-up voltage at the gates of the transistor level shifters, the DBG_PWR_BTN#, DBG_FORCE_OFF#, DBG_RESET#, DBG_RECOVERY#, and the FTDI_JTAG_TRST# signals can get unintentionally triggered when connecting a cable to the USB-C connector of the FTDI debug port. This may reset or shut down the module, or shut down the power rails of the carrier board.

Workaround: Connect the cable to the USB-C connector of the FTDI debug port before powering on the carrier board. As an alternative solution, the resistors R102, R109, R115, R120, and R245 can be replaced with resistors having a resistance of 1MOhm. This slows down the transistor level shifter circuits and makes sure that the power control signals are not triggered when connecting the cable to the USB-C connector of the FTDI debug port. The same improvement is going to be implemented in future versions of the product.

Description: The 10k pull-down resistors R251 and R254 connected to the pins 26 and 24 of the audio codec (IC28) affect the functionality of the device’s internal multiplexers and signal amplifiers. The analog input pins of the audio codec shift the input DC offset to their internal virtual ground VMID. The external pull-down resistors are affecting this DC offset, causing the opening of the internal multiplexer’s analog signal switches and the saturation of the amplifier's outputs. This leads to the distortion of the "Line In" signals (only the positive polarity parts of the input signals are recorded) and crosstalk from the "Line In" input to the "Mic In” input.

Workaround: Remove the pull-down resistors R251 and R254 from the carrier board. This makes the audio codec’s "Line In" and "Mic In” inputs work properly. Please see the PDF errata document in the "Errata/Known Issues" section for more information.

Description: Because of the unexpected behaviour of the Cypress USB-C PD detection chip, the Dahlia board is turning on even with an improper USB power source.

Workaround: Use the Dahlia Carrier board only with suitable USB power sources. Alternatively, USB Type-A to Type-C cables or adapters without a pull-up resistor on CC line can be used.

Description: The CTRL_FORCE_OFF_MOCI# input on the Dahlia carrier board features a 1MΩ pull-down resistor instead of a pull-up resistor. In the Verdin family definition, the CTRL_FORCE_OFF_MOCI# signal is specified as open-drain signal that is 5V tolerant. The pull-up resistor is supposed to be on the carrier board. Without this pull-up resistor, the CTRL_FORCE_OFF_MOCI# remains low and therefore is asserted all the time. The CTRL_FORCE_OFF_MOCI# signal is permanently pulling down the kill input of the power button IC LTC2954 (IC10). The LTC2954 ignores the kill input for the first 512ms after turning on. After this internal timer is expired, the kill signal will power off the system. This means pressing the power button on the Dahlia carrier board will turn on the power only for 512ms.

Workaround: Removing R96 disables the CTRL_FORCE_OFF_MOCI# signal on the Dahlia carrier board. However, this disables the “kill-feature” entirely. Therefore, after a shutdown, the main supplies are not turned off. For turning off the main power rails, the power button needs to be pressed for >7s. Besides this inconvenience, the modification is compatible with all Verdin module versions.

Description: The ADC input sampling time can be set between 3 and 131 clocks (of the 24MHz used). According to the ADC datasheet, at the longest sampling time of 131 clocks, the source output resistance must not be higher than 5kOhm. The resistor value assembled on the affected product version was 10kOhm. This leads to the sampling capacitor not being fully charged to the input voltage and thus inaccurate ADC conversion results. In the fixed product versions, the series resistors value has been changed to 1kOhm.

Workaround: None.

Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, the eMMC firmware will lock up the device, not allowing any further writes to the eMMC. The theoretical lifetime data write capacity for SkyHigh eMMCs in pSLC mode would be 60TB. By default, Toradex doesn't enable the pSLC mode and therefore doesn't run into this problem.

Workaround: SkyHigh implemented an FW fix. Customers using pSLC mode and writing more than 32TB during the lifetime of the product can execute a single-step FW update: https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc Products produced after 09.12.2022 are not affected

Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and writing more than 32TB to the eMMC, the eMMC firmware will lock up the device, not allowing any further writes to the eMMC. The theoretical lifetime data write capacity for SkyHigh eMMCs in pSLC mode would be 60TB. By default, Toradex doesn't enable the pSLC mode and therefore doesn't run into this problem.

Workaround: SkyHigh implemented an FW fix. Customers using pSLC mode and writing more than 32TB during the lifetime of the product can execute a single-step FW update: https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc Products produced after 09.12.2022 are not affected

Description: During a software initiated reset cycle, the nRESET_OUT signal is not asserted on the Colibri iMX6 V1.0 module. Unlike other Colibri modules, the nRESET_OUT signal remains the whole time high during the software initiated reset. During power up as well as hardware initiated reset cycles (by pressing the nRESET_IN/RESET_EXT button), the nRESET_OUT signal gets asserted similar to other Colibri modules. This is not an issue as long as external peripheral devices on the carrier board do not need to be reset during a software reset or no software initiated reset cycles are used on a system.

Workaround: A possible workaround is implementing a small reset circuit on the carrier board that allows driving low the reset signal by using any free GPIO. Since on the Colibri iMX6 the reset state of regular GPIOs is configured as input with enabled internal pull up resistor, the transistor will pull down the reset line during a software initiated reset cycle. The bootloader or application needs to reconfigure the GPIO as output and drive it low for releasing the external reset signal.

Description: Under high load, an audible hissing noise may be heard from the power supply, linked to its operational switching frequency. This occurs when powering the board through either the USB-C power delivery or the terminal block.

Description: The Schmitt-trigger inverter connected to the UART_2 interface is improperly routed, rendering the onboard RS485 interface non-functional.

Workaround: Use the jumper section to access the UART_2 interface and connect it to an external RS485 converter circuit.

Description: On the Aquila Development Board, the pull-up resistors of the SDA and SCL lines of the I2C_3_DSI bus are merged in the jumper area. This means that the resulting pull-up resistance on the bus is ~0.935kOhm instead of 1.87kOhm, which may be too low for some displays, making it impossible to read the EDID.

Workaround: If the bus resistance on the I2C_3_DSI bus seems too low, remove resistors R209 and R211.

Description: The Ethernet interface on the module uses the 25MHz clock directly from the SoC. The jitter introduced by the clock is too high to pass Ethernet Compliance.

Description: The USB_2_SS_TX lines lack the required 100nF serial capacitors. The Aquila Development Board V1.2 addresses this by replacing the R461 and R462 resistors with capacitors. Customers should account for this limitation when designing custom carrier boards for the AM69 revision.

Workaround: When designing custom carrier boards for the AM69 V1.0 revision, customers must include 100nF serial capacitors on the USB_2_SS_TX lines. These capacitors can later be replaced with 0R resistors to ensure compatibility with future AM69 module revisions.

Description: On 07.07.2020 we were informed about an LVDS instability issue (flickering) on new version of NXP i.MX8QM/iMX8QP which are used in our prototype Apalis iMX8 products until version 1.1.B. NXP stated that “This failure causes information to be displayed blurry or with the wrong color on the screen. Potentially the screen may be observed to go black, which the driver can perceive as the screen not working.”

Workaround: We are working with NXP to get screened processors that do not manifest this issue. This issue will be fixed in the next product version.

Description: Apalis Evaluation Board (V1.1 and V1.0) power supply is designed to supply a maximum output current of 5A at 3.3V rail (Evaluation Board V1.1) and 3.3A at 3.3V rail (Evaluation Board V1.0). The buck converter on the Apalis Evaluation Board features Output Over-Current Protection (OCP), which shuts down the power supply immediately if the output current exceeds the maximum output current limit. The peak current consumption of the Apalis iMX8QM or Apalis TK1 V1.0 module can be higher than 5A under stress conditions like processor / GPU intensive tasks. Under such conditions, Apalis Evaluation Board power supply might shut down due to OCP limits. A higher continuous current also results in rise in temperature of the carrier board near the power supply region, which affects the current sense resistor value and lead/solder-joint resistance. Customer who are evaluating / testing Apalis iMX8QM or Apalis TK1 (V1.0) module with Apalis Evaluation Board carrier board can use the below mentioned workaround. We will develop a new power supply for Apalis Evaluation Board which addresses this issue.

Workaround: In order to run the Apalis iMX8QM or Apalis TK1 (V1.0) module on the Apalis Evaluation Board, the module performance need to be reduced by making sure that the CPU is not fully loaded while the GPU is extensively used. As a temporary workaround for evaluation/testing purposes, it is possible to increase the output current of the power supply by changing the current sense resistor (R44) on the Apalis Evaluation Board (V1.1 and V1.0). A 0Ω (zero ohm) sense resistor can be used to set the output current to maximum, only under lab/evaluation conditions. Please check the current rating of the inductor (L21) and ensure that the output current of the power supply doesn’t exceed the rating of the inductor. With the proposed workaround, the buck converter could be thermally overloaded due to higher continuous (average) current, which may result in overheating or failure of some components on the Evaluation Board. If required it is OK to change the current sense resistor in the lab. However, we don't recommend such changes in the field.

Description: Fixed in: 01192002 Analogue Camera Adapter V2.0C
When the Analogue Camera Adapter is connected to the Apalis Evaluation Board in combination with an Apalis iMX6 module, in some limited cases the obtained picture shows quality issues. The problem was mostly seen with Apalis Evaluation Board in combination with Apalis iMX6 modules, but it could also show with other combinations or custom carrier boards. This is due to low signal drive strength of the data signals. In V2.0B series resistors R22 and R33 have been changed from 47R to 22R (Resistor 22 ohm 63mW 5% 0603) to improve the signal quality. In some limited cases the signal strength still may be still too low. That is why we additionally shortened the cable to 50mm in V2.0C.

Workaround: Use a ribbon cable with lenght of equal or less then 70mm to connect the Analogue Camera Adapter to the Apalis Evaluation Board.

Description: Missing pullup’s on CAN SPI MISO signals might cause signal flickering. This could result in unecessary higher current consumption.

Workaround: There is no software or hardware workaround available for V1.0 modules. A weak external pullup will be added to V1.1 modules in order to avoid the MISO signal to float.

Description: The dedicated reset input of the boot eMMC on the module is not connected to the SoC. Therefore, the eMMC can only be reset by a power-on reset.

Workaround: If the eMMC needs to be reset, a complete system reset needs to be performed which includes a power cycle that triggers the power-on-reset of the eMMC.

Description: Due to back feeding, the CTRL_PWR_EN_MOCI can have a residual voltage. This means the voltage remaining at CTRL_PWR_EN_MOCI can be too high (>0.3V) which can be interpreted as a high state by some input circuits.

Workaround: Make sure the input low threshold for the circuits that are connected to the CTRL_PWR_EN_MOCI signals are high enough or use the CTRL_FORCE_OFF_MOCI# for disabling the power rails in power-off-state.

Description: During a reset cycle the CTRL_PWR_EN_MOCI signal can go to an undefined state. For some time, the signal can be neither high nor low.

Workaround: If a defined state of the CTRL_PWR_EN_MOCI is required during the reset cycle, use a comparator circuit.

Description: The product name printed on the PCB contains NFF instead of Verdin.

Description: The part KSZ9031RNXIC has been assembled instead of KSZ9131RNXI that is indicated in the product datasheet.

Workaround: Not available.

Description: The signal type of the CTRL_FORCE_OFF_MOCI# has been changed from 1.8V push-pull to a 5V tolerant open-drain. The reason is to simplify the carrier board design and to omit the need for a level shifter on the carrier board.

Workaround: On Verdin Development Boards, it is possible to remove the jumper for the CTRL_FORCE_OFF_MOCI# signal (pin A23 an B23 of X6). On the Dahlia carrier board, remove resistor R247. However, both workarounds disable the "kill-feature". Therefore, after a shutdown, the supplies are not turned off.

Description: The position of LED21, LED22, LED23, LED24 in the general-purpose LEDs and Switches area is not consistentwith the order of related signals available on the connector X38.

Workaround: Users should check table 3.14.2.1.5 of the product datasheet to avoid confusion when using this product feature.

Description: The last three bits of the PHY address are strapped by the PHYAD0, PHYAD1, and PHYAD2 pin. PHYAD0 and PHYAD1 are located on the LED output signals, which are strapped correctly. PHYAD2 is located on the RXC pin of the PHY (ETH_2_RGMII_RXC signal). The strapping resistors R188 and R189 are both missing in the BOM. Intended by design is to strap the signal high by assembling R188. Since both strapping resistors are missing, the strapping value is dictated by the module’s behavior of the ETH_2_RGMII_RXC signal during the enabling of the Ethernet power rails. The Ethernet power rails are enabled on the carrier board by the PWR_CTRL_4 signal. The Verdin iMX8M Plus has a weak pull-down enabled on the ETH_2_RGMII_RXC by default. Therefore, the PHY address gets strapped to 0b00011 rather than the intended 0b00111. In this case, the module can only communicate over the MDIO interface with the PHY if the driver changes the address to 0b00011.

Workaround: The best workaround is to populate R188 with a 10kΩ resistor. The resistor is a 0603 type. See Errata #5 of the Verdin Development Board errata for more information.

Description: SDIO interface is failing when SDIO evaluation kits are used in HS400 mode. By default, the software initiates communication in HS400 mode, which uses a 200MHz clock on the SD_1_CLK signal; this results in a failed tuning test. If a mode with lower frequencies is forced, the cards are working fine. This is caused by a signal integrity issue concerning the clock signal of the SDIO interface.

Workaround: There is no fix for this issue at the moment. SDIO evaluation kits might need to be used at lower frequency modes.

Description: We need to create public packages for the Apalis Evaluation Board and add them to the GIT repository.

Description: The POWER_ENABLE_MOCI signal is intended to be used for switching the peripheral voltage rails on the carrier board, like the 5V_SW and 3.3V_SW on the Ixora. Depending on the amount of backfeeding over the interface signals from the carrier board to the Apalis iMX6 module, the POWER_ENABLE_MOCI signal can remain between 1.0V and 1.4V in module shutdown. Depending on the carrier board circuit, this can be too high for turning off the peripheral voltage rails. For example, on the Ixora V1.2, a different buck converter for the 5V_SW is used than on the previous versions. The threshold voltage for the enable signal is lower on the new buck converter. Depending on the backfeeding level, the 5V_SW buck converter does not get disabled in the shutdown state. The Ixora V1.0 and V1.1 are not affected by this issue since they have been using a different buck converter with a higher threshold.

Workaround: Add a circuit to the carrier board for increasing the POWER_ENABLE_MOCI threshold voltage to between 2.0V and 2.5V. This could be achieved by adding a comparator or similar circuit. Such a solution is implemented in the V1.3 revision of the Ixora. A simple voltage divider added to the POWER_ENABLE_MOCI signal can shift the voltage levels. Important: make sure that the minimum input voltage for enabling the buck converter is still guaranteed. With the AOZ2260 buck converter (which is used on Ixora V1.2), a 10k/10k voltage divider can be a suitable option. For patching such a divider, replace R15 with a 10k 0603 resistor and add another 10k resistor from the PMIC_EN_5V signal to the ground.

Description: In some cases, the recovery button of carrier boards needs to be pressed for 6-10s after powering up the SoM to get it into Recovery Mode. In other cases, the SoM does not go into recovery mode at all, even after the 6-10s period has elapsed. The issue is caused by the combination of the NXP i.MX8 SoC's boot ROM code and the behavior of the USB interface of the host computer the USB OTG port of the carrier board is connected to. On the SoC side, at power-up, a boot monitor timer is initialized. During USB enumeration in serial download mode, the host side may enumerate multiple times until enumeration succeeds. The enumeration retries take time and result in a delayed entry into Recovery Mode. In some other cases, the maximum number of enumeration retries may get exceeded, which results in an enumeration failure. Under corner conditions, the ROM code may not be able to refresh the boot monitor timer due to the behavior of the USB host, causing a device system reset.

Workaround: In general, changing to a different host is the most effective way to avoid the issues. NXP may potentially fix this issue in the future.

Description: The STMPE811 ADC and touch controller IC uses the IN0_GPIO1 pin for strapping between I2C and SPI mode. If the pin is high during the power-up of the controller, the chip gets misconfigured as an SPI device. In this case, the chip cannot be accessed over the I2C mode and is unavailable. The IN0_GPIO1 is used as ADC_AD1 input of the module (edge connector pin 6). A voltage applied to the analog input ADC_AD1 during the module's power-up can cause the ADC and touch controller to be strapped wrongly and therefore not accessible. The Colibri T30 features a circuit that pulls down the ADC_AD1 input during the reset state to prevent false strappings. However, this circuit may not work correctly if there is extensive backfeeding to the Colibri T30 module. The best prevention is not applying any voltage to the ADC_AD1 input while the module is not powered.

Workaround: Ensure that there is no voltage applied to the ADC_AD1 input until the module booted. Use any of the other ADC inputs instead.

Description: The STMPE811 ADC and touch controller IC uses the IN0_GPIO1 pin for strapping between I2C and SPI mode. If the pin is high during the power-up of the controller, the chip gets misconfigured as an SPI device. In this case, the chip cannot be accessed over the I2C mode and is unavailable. The IN0_GPIO1 is used as ADC_AD1 input of the module (edge connector pin 307). A voltage applied to the analog input ADC_AD1 during the module's power-up can cause the ADC and touch controller to be strapped wrongly and therefore not accessible. The module features a circuit that pulls down the ADC_AD1 input during the reset state to prevent false strappings. However, this circuit may not work correctly if there is extensive backfeeding to the module. The best prevention is not applying any voltage to the ADC_AD1 input while the module is not powered.

Workaround: Ensure that there is no voltage applied to the ADC_AD1 input until the module booted. Use any of the other ADC inputs instead.

Description: Due to the Microchip KSZ8041NL Ethernet PHY errata, the Ethernet can become unusable after exiting the power save mode. The Ethernet PHY is powering down the PLL during the software power down, which can create problems. The issues only appear under certain circumstances and in certain temperature ranges. The issue cannot be reproduced with all modules.

Workaround: Microchip is recommending not using the software power-down of the Ethernet PHY. This means the Ethernet PHY should be left running even in the module's power save (suspend) mode. However, this increases the module's power consumption in the power save state.

Description: The VCC_BATT input of the module (pin 40) powers the SNVS rail of the SoC. Besides the RTC and power management function, the i.MX 6ULL SoC uses this rail also as IO rail for the pins in the SNVS block (SNVS pins). Some of these interface pins are available on the SODIMM connector as regular GPIOs (SODIMM pin 43, 45, 93, 95, 105, 107, 127, 131, 137, and 138). Since the VCC_BATT on the Colibri standard is meant to be used as RTC battery input and not for powering IO rails, a power rail switch is added to the module. If the module is powered up, the VCC_BATT rail is connected to the 3.3V rail.

Description: The current consumption on the RTC battery rail (VCC_BATT) can reach up to 240 µA on earlier modules if the primary voltage rail (3V3) is not applied. The issue affects the Colibri T30 1GB V1.1E and older, but does not affect the Colibri T30 1GB IT. Even though the current consumption is reduced to 56 µA on newer versions of the module, it is recommended to use an external ultra-low power RTC device if the system time needs to be retained without the presence of the primary voltage rail.

Workaround: Use an external ultra-low power RTC device (see the Colibri Evaluation Board for reference).

Description: The boot process might hang with the following error on 512MB module variant: ``` U-Boot SPL 2023.04-6.4.0-devel+git.96179e4a5bb0 (Sep 06 2023 - 06:13:04 +0000) SYSFW ABI: 3.1 (firmware rev 0x0009 '9.0.7--v09.00.07 (Kool Koala)') WARNING: Less than 64MB RAM detected ```

Workaround: Reset the board.

Description: The version of the product is wrongly presented on the configblk of the versions without level shifter. It is recommended to rebuild the configblk in case the version written there is being used for any purpose in the application.

Workaround: Re-do the congifblk using uboot commands

Description: 1. Check PMIC-GPIO testability 2. Check PMIC_LPM_EN0 connections and PARTIAL I/O power topology

Description: On the MIPI CSI-2 interface used on the Verdin Development Board V1.1A, all of the single-ended signals are at 3.3V level, except for the CSI_1_MCLK signal (pin #12 of X47), which is at 1.8V level.

Workaround: In case a MIPI CSI-2 camera requires the CSI_1_MCLK signal (pin #12 of X47), and in case it requires this signal to be at 3.3V level, it could be level shifted on custom carrier boards.

Description: The Verdin pinout contains an optional master clock output for the CSI_1 interface. The SAI3_MCLK SoC pin is used for providing the optional Verdin camera interface master clock CSI_1_MCLK output. This signal is available on the module edge connector pin 91. The SoC pin can provide clock signals from the SAI3 and SAI5 audio interfaces. Therefore, a dummy audio driver with a dummy audio stream would be required for enabling the clock output. The current Toradex BSP does not support the CSI_1_MCLK option.

Workaround: Instead of using the CSI_1_MCLK, use an external crystal or oscillator for the camera. The i.MX 8M Mini SoC features two general-purpose clock outputs that can be used independently from the audio interfaces. Those clock signals are only available as alternate functions of other signal pins. Therefore, the clock signals are not compatible with other Verdin modules. If one of the general purposes clock outputs are used, adding an assembly option for using the CSI_1_MCLK pin is highly recommended. This ensures compatibility with existing and future versions of the Verdin iMX8M Mini and other Verdin modules.

Description: The KSZ9131 Ethernet PHY on the Verdin modules has two LED outputs (ETH_1_LED_1 and ETH_1_LED_2) which are used for indicating the link and activity statuses on the bus. These LEDs are available on pin 235 and 237 of the module edge connector, respectively. ETH_1_LED_1 (pin 235) is intended to indicate the activity status, while ETH_1_LED_2 (pin 237) is intended to indicate the link status. On the PCB versions 1.0 and 1.1, these two signals are swapped. In the next revision of the carrier board PCB, the connections will be corrected. In the Verdin Development Board datasheet, the corrected connections are shown.

Workaround: For custom carrier board designs, the correct LED connections should be implemented. A potential workaround could be flipping the roles and behavior of the LED outputs of the on-module Ethernet PHY in software. However, this is not supported by the related driver.

Description: The pin configuration registers of the i.MX8 SoC have reset states. These reset states have been stated in the Toradex Apalis iMX8 datasheet (document revision 1.1 and earlier) as reset states in section 4.4. However, the i.MX 8 SoC features a System Controller Unit (SCU) that handles all of the pin configurations. The SCU comes with a firmware (SCFW) that has its own default pin configurations. By the time of the release of the RESET_MOCI# signal, the SCU already overrides the pin configurations. Therefore, the SCU default settings are the relevant reset states for the pins. In case of some of the GPIO-capable pins, the SCFW reset states are different from the register reset states. A comparison list can be found in this article: https://developer.toradex.com/knowledge-base/reset-state-of-the-imx8-soc-pins. The Apalis iMX8 datasheet (document revision 1.2 and newer) has been updated with the reset values dictated by the SCFW. Despite the original intention, the USBO1_EN and the USBH_EN have pull-up resistors enabled instead of being pulled down during reset. This means that the USB power rails can get unintentionally enabled in the reset state of the module. Depending on the carrier board, the different reset states of the SoC pins can result in unintended behavior. For example, on the Ixora carrier board V1.2A, the MMC1_D5 (pin 152) and MMC1_D6 (pin 156) are used for driving LEDs. By default, these two pins have pull-up resistors enabled instead of the pull-down. Therefore, the LEDs are lit during the reset cycle.

Workaround: The values of the internal pull-up and pull-down resistors of the SoC are between 15kΩ and 50kΩ. These pull resistors can be disabled in the bootloader or during kernel boot. The issue caused by the unintentional pull-resistor states persists in time between the release of the reset signal and the bootloader configuring the IO pins in the intended state. In that case, an external pull-resistor on the carrier board can resolve the issue. According to measurements, adding a 10k pull-down resistor to a GPIO-capable pin with an internal pull-up resistor enabled results in a voltage level of around 0.6V. With an external 1k pull-down, the level goes below 100mV. However, these are just typical values at room temperature. For the USBO1_EN and the USBH_EN signals, it is recommended to add a 10k pull-down resistor (or replacing the existing weak pull-down resistor). This keeps the power enable signal level below the maximum input low threshold of the USB power switch IC during the reset cycle.

Description: In some cases, the recovery button of carrier boards needs to be pressed for 6-10s after powering up the SoM to get it into Recovery Mode. In other cases, the SoM does not go into recovery mode at all, even after the 6-10s period has elapsed. The issue is caused by the combination of the NXP i.MX8X SoC's boot ROM code and the behavior of the USB interface of the host computer the USB OTG port of the carrier board is connected to. On the SoC side, at power-up, a boot monitor timer is initialized. During USB enumeration in serial download mode, the host side may enumerate multiple times until enumeration succeeds. The enumeration retries take time and result in a delayed entry into Recovery Mode. In some other cases, the maximum number of enumeration retries may get exceeded, which results in an enumeration failure. Under corner conditions, the ROM code may not be able to refresh the boot monitor timer due to the behavior of the USB host, causing a device system reset.

Workaround: In general, changing to a different host is the most effective way to avoid the issues. NXP may potentially fix this issue in the future.

Description: The module features a LM95245 temperature sensor that monitors the die temperature of the SoC and the local temperature of the temperature sensor itself (the latter used for representing the PCB temperature). By default, the over-temperature limit of the local temperature sensor is set to 85°C. This temperature threshold is set to a higher value during the boot process (to actually allow for booting at an ambient temperature of 85°C, assuming an even higher PCB temperature). However, if the ambient temperature is already 85°C during the power-up of the module, the over-temperature output of the LM95245 (connected to the power disable input of the PMIC) may get triggered before the threshold gets updated. In this case, the SoM power supply is shut down immediately. This also removes power from the temperature sensor, which allows the PMIC to reenable the power rails. This cycle repeats until the local temperature falls below the default over-temperature threshold of 85°C.

Workaround: Make sure that the module gets powered up at an ambient temperature of 80°C or lower.

Description: The Microchip KSZ8041 Ethernet PHY has an errata: https://ww1.microchip.com/downloads/en/DeviceDoc/80000700A.pdf. According to the second item in the document, a small percentage (less than 1%) of the devices can potentially fail to properly read the strapping pins and set the intended configuration if the 3.3V supply rail rises too fast. On the Colibri iMX6ULL SoM, the 3.3V power rail for the Ethernet rises faster than the required 250us. Therefore, on rare occasions, a small amount of Colibri iMX6ULL SoMs may fail to communicate with the Ethernet PHY after power-up. If the strapping of the PHY configuration fails, the system cannot communicate with the PHY over the MDIO interface. The Ethernet port is not working in this case. According to our tests, the issue mainly appears on the affected modules if the power is enabled at extremely low temperatures (below -30°C). The pull-up resistors of the Ethernet LEDs on the carrier board can backfeed to the 3.3V Ethernet power rail on the module. This backfeeding actually reduces the risk of strapping failures.

Workaround: There is currently no permanent workaround. If the Ethernet PHY is not accessible, try to power cycle the Ethernet PHY or the complete Colibri SoM. Disabling the RMII clock turns off the Ethernet power rails. Try waiting at least 1 second before reenabling the RMII clock and initializing the Ethernet PHY.

Description: Some Apalis iMX8 product configurations feature a Wi-Fi/Bluetooth module. The module featured on the System-on-Module (SoM) is limiting the effective operating temperature range of the product to -30C...85C. When powering up/booting the SoM at ambient temperatures of -30C and below, the Wi-Fi/Bluetooth module may fail to start and function properly. As the Wi-Fi/Bluetooth functionality is not considered boot-critical, the SoM may still be used throughout the full specified temperature range (-40C...85C). When powering up/booting the SoM at ambient temperatures of -30C and below, the warming up the Wi-Fi/Bluetooth module (by the heat dissipated by the other components) may eventually result in the Wi-Fi/Bluetooth module starting and functioning properly.

Workaround: Power up/boot the SoM at ambient temperatures of -30C or above. If this is not feasible, monitor the status of the Wi-Fi/Bluetooth module in software after powering up/booting the SoM, and reset the SoM in case the Wi-Fi/Bluetooth module failed to start/initialize properly. The reset could be initiated both in software and hardware. Repeat this procedure until you have a functional Wi-Fi/Bluetooth module.

Description: The circuit used to generate the CTRL_PWR_BTN_MICO# on the computer module is affected by a hardware bug that could cause this signal to be triggered involuntarily by a fast change in the input voltage. The Voltage needs to increase immediately by at least by 0.9V to trigger the signal. The CTRL_PWR_BTN_MICO# allows the implementation of a power button behavior like the ones used on regular personal computers and smartphones. Short pressing the power button powers up the system from the “Module OFF” state or wakes the system from the sleep state. If the module is running, short pressing the power button generates a software interrupt. Depending on the operating system settings, this starts a software shutdown or opens a menu that lets the customer decide what to do.

Workaround: The best way to mitigate this issue is to configure the CTRL_PWR_BTN_MICO# differently in the software. If this is not possible and it is necessary to test the behavior of a module where this issue has been fixed, please contact the support team. Future versions of this product will have a different assembly option that will solve this bug completely.

Description: The nRESET_EXT (reset input of the module, pin 26) features a debouncing circuit since it is allowed to connect directly a reset button to this pin. The debouncing circuit delays the reset by around 30ms. During a regular power up sequence, the nRESET_OUT (reset output of the module, pin 87) is released also at around 30ms. If the nRESET_EXT pin is hold down during the power up, the two delays are racing. If the debouncing circuit wins, everything is OK, the nRESET_OUT remains until the nRESET_EXT is released. However, if the debouncing loses the race, there can be as short peak on the nRESET_OUT. Whether this peak appears or not as well as the duration depends on different factors. It is depending on the tolerances of the debouncing circuit and therefore can appear on certain modules more often than on others. It also depends on the module temperature and whether an RTC battery is present or not.

Workaround: The Colibri iMX6 module as well as most of the peripheral devices are not affected by the possible nRESET_OUT pulse. This means in most of the cases, the issue can be ignored. For peripherals that relay on a single reset release during the power up sequence, an additional circuit is required on the carrier board. Such a circuit can be a simple AND gate with the NRESET_OUT and nRESET_EXT as inputs can be used.

Description: These errata are actually NXP errata affecting all i.MX and Vybrid processors. There are two issues in the boot ROM when using the processors in a security-enabled configuration (SEC_CONFIG[1] eFUSE is programmed). By default, this fuse is not programmed on Toradex modules. Customers not fusing this setting are therefore not affected by these issues. Customers using the security-enabled configuration are affected by these issues. More information can be found in the respective NXP errata documents: https://docs.toradex.com/104705-err010872-secure-boot-vulnerability-erratum-preliminary-rev0.pdf https://docs.toradex.com/104706-err010873-secure-boot-vulnerability-erratum-preliminary-rev0.pdf

Workaround: Please refer to the documents mentioned above for workarounds.

Description: On Verdin iMX8MM USB_1 port is operating as dual-role-port for both host and client functions. We have seen during client mode USB Vbus detection fails occassionally due to slow rise of 5V on VBus pin. This result in below error message: usbmisc_imx 32e40200.usbmisc: Error occurs during detection: -22 usbmisc_imx 32e40200.usbmisc: vbus is error We have seen no impact due to this on USB functionality in any way.

Workaround: Not applicable as voltage stabilizes and there is no impact on USB functionality.

Description: It's not possible to draw 3A from the 5V rail with an input voltage of 8V.

Workaround: Recommended input voltage should be higher than 11V. It will be fixed in the next version of the Ivy plus

Description: When configuring and using the SkyHigh eMMC in pSLC (pseudo-SLC) mode and trying to boot from SD card the module may not work.

Workaround: There are three possible workarounds: 1) Access the eMMC from U-Boot before launching the Kernel by using the following command: ls mmc 0.4:0 /boot 2) Update the eMMC firmware according to the instructions: https://developer.toradex.com/linux-bsp/how-to/hardware-related/firmware-update-skyhigh-emmc 3) Modules produced after 09.12.2022 are not affected